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phy1071 - 01 - rd - 1. 2 released datasheet page 1 1 25m bps C 2 .12 5g bps vcsel driver / post amp with digital diagnostics features ? multi - rate from 1 25m bps to 2 .125 gbps ? vcsel driver output stage with 16 ma max modulation drive and 20 ma bias current ? p rogrammable mean power contr ol loop ? temperature compensated modulation current ? integrated limiting amplifier with selectable swing cml output to reduce radiated emissions ? programmable receiver low pass filter ? integrated l oss o f s ig nal function ? digital diagnostic mode compliant with s ff- 8472 using an external mcu ? stand - alone mode where device parameters are loaded from an external eeprom ? - 40c to +85c operating range ? 36pin 6mm x 6mm qfn package ? eye safety logic applications ? sonet, fibre channel, gbe ? sff and sfp modules low pass filter rxout+ rxout- rxin+ rxin- txin+ txin- vcsel+ vcsel- tx_disable los vcsel_bias tx_fault mpd internal registers & 2 wire i/f scl sda sa_scl safety logic sa_sda mean power control loop modulation temperature comp tsense driver o/p level detect ref rssi ref voltage reg mux shutdown descrip tion the phy1071 - 01 is a combined vcsel driver and limiting amplifier with support for digital diagnostic monitoring for use within small form factor modules for fibre channel applications. the transmitter integrates a high speed output stage with programmable bias and modulation currents , controlled through a 2 - wire serial interface. the mean power control loop allows connection in both common cathode and common anode configuration s. a loss of signal (los) detector is included with detection based on either the receiver photo detector average current or received signal modulation amplitude. when us ed in digital diagnostics mode the integrated a/d converters measuring temperature, t x bias, supply voltage, rx signal strength and mean power are read via a 2 - wi re serial interface. an external microcontroller unit ( mcu ) is used for calibrating real time diagnostic monitors and alarm generation. ratesel qfn36 sa_sda 1 9 reset vss_rx rxout+ rxout- sda rref vdd_txvcsel- vss_tx vss_txvdd_txo vcsel_bias sa_scl vdd_rxo vdd_rx vss_rx rxin+ rxin-los shutdown tsense rssi nc tx_fault tx_disable txin+txin- vss_tx vss_tx mpd scl vggvcsel+ vdd_tx 1018 19 27 28 36 phy1071 - 01 figure 2 - device pin out (top view) figure 1 - outline block diagram a maxim integrated products brand 19 - 56 82 ; rev 3 /1 2 downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 2 table of contents 1. ordering information ................................................... ................................................... .............................. 3 2. pin description ................................................... ................................................... ....................................... 3 3. key specifications ................................................... ................................................... .................................. 5 3.1. absolute maximum rating s ................................................... ................................................... .......... 5 3.2. continuous ratings ................................................... ................................................... ....................... 5 3.3. receiver ................................................... ................................................... ........................................ 5 3.4. transmitter ................................................... ................................................... .................................... 7 3.5. 2- wire serial interface ................................................... ................................................... .................. 9 3.6. dc characteristics: tx_fault; tx_disable; los. ................................................... ................... 10 3.7. typical operating characteristics ................................................... .................................................. 11 4. functional description ................................................... ................................................... ......................... 12 4.1. overview ................................................... ................................................... ..................................... 12 4.2. receiver features ................................................... ................................................... ....................... 13 4.3. transmitter features ................................................... ................................................... ................... 16 4.4. vcsel safety features ................................................... ................................................... .............. 18 4.5. tsense temperature sensor ................................................... ................................................... ...... 20 5. control interface ................................................... ................................................... .................................. 21 5.1. memory map ................................................... ................................................... ............................... 21 5.2. operation ................................................... ................................................... ..................................... 22 5.3. digital diagnostics mode ................................................... ................................................... ............. 27 5.4. stand - alone mode ................................................... ................................................... ...................... 29 5.5. 2- wire serial interface ................................................... ................................................... ................. 31 6. register map ................................................... ................................................... ........................................ 33 7. simplified interface models ................................................... ................................................... .................. 42 8. typical applications ................................................... ................................................... ............................. 44 8.1. power supply connections ................................................... ................................................... ......... 45 9. packaging ................................................... ................................................... ............................................ 47 10. contact information ................................................... ................................................... .............................. 48 downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 3 1. ordering information part number description package phy1071 - 01 qd- rr enhanced 2 g vcsel driver and post amp qfn36, 6mmx6mm in tape and reel, rohs compliant (see figure 43, p. 47 ) phy1071 - 01 qs- rr not for use in new designs enhanced 2 g vcsel driver and post amp qfn36, 6mmx6mm in tape and reel , rohs compliant ( see figure 43, p. 47 ) 2. pin d escription pin no name direction type description 1 sa_sda p 1 ,4 p i/o lvttl 2-wire serial interface. connects to eeprom in stand alone mode 2 reset i/p cmos reset 3 vdd_rxo p 2 p power limiting amp lifier output power supply 4 vss_rx p 3 p g rou nd receiver section ground connection 5 rxout - o/p cml limiting amplifier differential serial data output. 6 rxout+ o/p cml limiting amplifier differential serial data output. 7 sda p 4 p i/o lvttl 2-wire serial data interface. used in digital diagnostics mode. 8 scl p 4 p i/p lvttl 2-wire serial interface clock. used in digital diagnostics mode. 9 rref i/p analog connect to ground through a 10k resistor 10 tx_fault o/p lvttl (open collector) transmit fail alarm. a logic 1 indicates a fault in the transmission system. requires external pull up for sfp msa compliance 11 tx_disable p 4 p i/p lvttl output disable (active high). disables vcsel drive. on chip 8k pull up 12 vss_tx p 3 p g rou nd transmission circuitry ground connection 13 txin+ i/p cml differential vcsel driver input from host 14 txin - i/p cml differential vcsel driver input from host 15 ratesel i/p lvttl toggles between two low pass filter characteristics. external 30k pull down resistor required for sfp msa compliance 16 vss_tx p 3 p g rou nd transmission circuitry ground connection 17 nc no connection. leave open circuit 18 mpd i/p analog monitor photodiode input 19 vcsel_bias o/p analog vcsel bias current output 20 vdd_tx p 2 p power transmission circuitry power supply connection downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 4 21 vdd_txo p 2 p power transmission circuitry power supply connection 22 vss_tx p 3 p g rou nd transmission circuitry ground connection 23 vcsel - o/p high speed vcsel differential driver output 24 vcsel+ o/p high speed vcsel differential driver output 25 vss_tx p 3 p g rou nd transmission circuitry ground connection 26 vgg g rou nd ground substrate connection 27 vdd_tx p 2 p power transmission circuitry power supply connection 28 shutdown o/p cmos gate drive for optional vcsel shutdown fet switch 29 tsense i/p analog external temperature sensing transistor connection 30 rssi i/p analog receive signal strength indicator & regulated supply for rx photodiode 31 los o/p lvttl (open collector) loss of signal output. requires external pull up for sfp msa compliance 32 rxin+ i/p cml limiting amplifier differential serial data input 33 rxin- i/p cml limiting amplifier differential serial data input 34 vss_rx p 3 p g rou nd receiver ground connection 35 vdd_rx p 2 p power limiting amp power supply 36 sa_scl p 1 ,4 p i/p lvttl eeprom 2 -wire serial interface clock - paddle g rou nd ground / thermal paddle 1 used in stand-alone mode only. 2 all vdds are internally connected by back-to-back protection diodes. vdds should not be powered up independently. 3 all vsss are internally connected to the ic substrate connection. 4 internally pulled high with an 8k? pull -up resistor. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 5 3. key specifications 3.1. absolute maximum ratings parameter conditions min typ max unit supply voltage - 0.5 +6.5 v voltage on any pin vss - 0.5 vdd + 0.5 v storage temperature 150 c soldering temperature for 25 seconds 260 c junction temperature 140 c esd human body model 2 kv under absolute maximum rating conditions device not guaranteed to meet specifi cations; permanent damage may be incurred by operating beyond these limits. 3.2. con tinuous ratings parameter conditions min typ max unit operating supply voltage continuous operation 2.97 3.3 3.63 v current consumption excluding bias & modulation at 10ma bias & 8ma modulation 102 ma operating temperature ambient still air , max bias and modulation current -40 25 +85 c 3.3. receiver 3.3.1. receive limiting amplifier parameter symbol conditions min typ max unit sensitivity differential, ber=1*10 p - 12 p <2.125gbps 5 7.5 mvpp max differential input overshoot and tj within spec 1200 mvpp input termination impedance differential rxin+ to rxin-, dc 100 ? input return loss differential, f<4ghz, device powered on 10 db output return loss differential, f<4ghz, device powered on 10 db low frequency cutoff high pass 3db point for rx system 15 khz output rise and fall times (20%-80%) slow, rx_sl ew = 1 120 160 ps fast , rx_slew = 0 60 80 differential output swing high swing mode p 1 p low swing mode p 1 p 700 370 900 470 mvpp total jitter, tj measured over rx input voltage range 100 mui pp output resistance rxout+/ - single ended to vdd_rxo 40 50 60 ? rate select change time t_ratesel using ratesel pin 10 s 1 receiver differential output swing characterised at 155mbps and 2 p 7 p -1 prbs using dca eye amplitude function downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 6 3.3.2. r ssi indicator and rx pd regulator parameter symbol conditions min typ max unit voltage on rssi pin ireg=2ma (10nf & 100 ? minimum load) 2.4 v current sourced by rssi pin measured using rx power adc 0 2000 a 3.3.3. receive photocurrent los parameter symbol conditions min typ max unit rssi los assert time 10 s rssi los de-assert time 40 s electrical hysteresis 20log b10 b (rssideassert / rssiassert) 2 4 db rssi los assert level range set by avg_los_set, address f4h 1.0 411 a 3.3.4. oma los parameter symbol conditions min typ max unit oma los assert time t_loss_on 100 s oma los de -assert time t_loss_off 20 s electrical hysteresis 20log b10 b (vdeassert / vassert) 2.5 5.5 db oma los assert level set by oma_los_set, address f3h 10 50 mv t_loss_on t_loss_off oma signal los figure 3 - oma los detection downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 7 3.4. transmitter 3.4.1. transmitter inputs pa rameter symbol conditions min typ max unit high-speed data input signal voltage p 1 p differential, ac -coupled, from 1 25m bps to 2.125gbps 200 1800 mvpp high-speed data input impedance differential, dc 80 100 120 ? input return loss differential, f<4ghz, device powered on 10 db input common mode return loss both inputs shorted together, measured using 25 ? ? source termination, 100mhz C 2.5ghz 10 db 1 p p differential inputs of up to 2400mv can be used without damage but performance specification is not guaranteed 3.4.2. vcsel driver parameter symbol conditions min typ max unit modulation current i b mod b 0.5 16 ma electrical 20% to 80% rise / fall time measured using 50 ? ? effective termination, ac and dc coupled applications 55 65 ps total jitter contribution measured over modulation current range 100 mui pp vcsel output compliance range allowed voltage for vcsel driver output pins in dynamic operation, referenced to ground (vss_tx) . 600 mv bias current output compliance minimum allowed voltage for pin vcsel_bias, referenced to ground (vss_tx) 300 mv 3.4.3. vcsel mean power control loop parameter symbol conditions min typ max unit bias current 0.1 20 m bias current off transmitter disabled 10 a max current at mpd pin sink current 2.6 ma turn on/off overshoot bias current overshoot, loop_bw=1 15 % apc -3db loop bandwidth f b loop_bw b loop_bw = 0 loop_bw = 1 5 15 khz bias loop settling time t_settle loop_bw = 0 loop_bw = 1 5 500 10 1000 ms s downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 8 3.4.4. eye safety internal fixed l imits operation outside these limits causes a tx_fault to be asserted parameter symbol conditions min typ max unit eye safety supply voltage range voltage on vdd_txo or vdd_tx 2.7 3.9 v rref pin voltage limit rref voltage applied to pin after calibration 0.9 1.1 v 3.4.5. fault timing parameter symbol condition min typ max unit time to initialize t_init from power on or application of vcc>2.97v during plug in 300 ms hard tx_disable assert time t_off time from rising edge of tx_disable to when the optical output falls below 10% of nominal 2 s hard tx_disable negate time t_on time from falling edge of tx_disable to when the modulated optical output rises above 90% of nominal 1 ms hard tx_fault assert time t_fault time from fault to tx_fault on 100 s tx_disable pulse width t_reset time tx_disable must be held high to reset tx_fault 5 s tx_fault deassert time t_faultdass time to deassert tx_fault after tx_disable 300 ms 3.4.6. diagnostic timing diagrams tx_fault vcc>2.97 tx_disablevcsel_bias t_init t_off t_on figure 4 - device turn on downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 9 tx_fault tx_disable vcsel transmitting t_fault occurrence of fault t_reset t_faultdass figure 5 - fa ult detection 3.5. 2- wire serial interface 3.5.1. ac electrical characteristics parameter symbol comment min typ max unit scl clock frequency f b scl b 0 100 khz low period of the scl clock t b low b 4.7 C s high period of the scl clock t b high b 4.0 C s set-up time for a repeated start condition t b su:sta b 4.7 C s hold time (repeated) start condition t b hd:sta b 4.0 C s data hold time t bhd: dat b 0 3.45 s data set-up time t b su:dat b 250 C ns rise time of both sda and scl signals t br b C 1000 ns fall time of both sda and scl signals t bf b C 300 ns set-up time for stop condition t b su:sto b 4.0 C s bus free time between a stop an d start condition t b buf b 4.7 C s output fall time from vihmin to vilmax tof 10pf < c b(1 ) < 400pf 0 250 ns capacitance for each i/o pin ci C 10 pf 1 c bb b = capacitance of a single bus line in pf. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 10 t hd:sta t su:sta t high t low t su:dat t hd:dat t r t f t su:sto t buf sda scl of t figure 6 - sda and scl bus timing 3.5.2. dc electrical characteristics parameter symbol condition min typ max unit low level input voltage v bil b - 0.5 0.3 vdd v high level input voltage v bih b 0.7 vdd vdd b b + 0.5 v low level o/p voltage v bol b 3 ma sink current 0 0.4 v i/p current each i/o pin i bi b 0.1vdd b b < v bi b < 0.9v dd -10 10 ma 3.6. dc characteristics : tx_fault; tx_disable; los . parameter comment min typ max unit lvttl voltage out high external 4.7k to 10k pull-up host vcc - 0.5 host vcc + 0.3 v lvttl voltage out low external 4.7k to 10k pull-up 0 0.5 v lvttl voltage in high internal pull-up 2.0 vdd + 0.3 v lvttl voltage in low internal pull-up 0 0.8 v r pull-up internal pull-up 6 10 k ? downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 11 3.7. typical operating characteristics 3.7.1. electrical receiver eye diagrams (3.3v; ta = 25 p o p c; prbs 2 p 7 p -1) figure 7 C 1.0625gbps high swing mode figure 8 C 2 .12 5gbps low swing mode 3.7.2. optical transmit eye diagrams (3.3v; ta = 25 p o p c; prbs 2 p 7 p - 1) trans mitter setup with p b mean b = - 4.5dbm; e.r. =8.5db; oma=500 w t fig 9 C 2 .12 5gbps; 60% margin t fig 10 C 2.125gbps; unfiltered rise and fall times 65ps downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 12 4. functional description 4.1. overview rssi ram vcsel safety 2-wire slave los agc receiver los cml rxin+ rxin- programmable lpf modulation dac mean power dac bias current vcsel+ vcsel- vcsel_bias mpd transmitter safety critical shutdown shutdown tx_fault control interface 2-wire master control registers controller tx_disable rxout+ rxout- txin+ txin- reset sda sa_sda sa_scl scl tsense rref temperature adc ratesel comp figure 11 - top - level block diagram of the phy 1071 - 01 downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 13 4.2. receiver features the receiver input is designed to be ac - coupled to the transimpedance amplifier, with internal 10 0 ? differential termination. the agc amplifier is followe d by a low - pass filter with programmable cut - off frequency, enab ling the phy1071 - 01 r eceiver to support five discrete data rates in the range 1 25/155 m bps to 2 .12 5 gbps . the filter output is followed by a limiting stage. for minimum duty cycl e distortion, dc feedback from the limiter output is used for offset cancella tion. the output cml buffer completes the receiver chain, delivering the output at pi ns rxout+ and rxout - . the output edge rate is dependent on the programmable filter setting. additionally, the output swing is programmable to satisfy different interface requirements (e.g. cml, ac - coupled lvpecl compatible). the phy1071 - 01 includes a regulator to deliver a controlled voltage to the receiver photodiode cathode at the rssi pin. t he current at rssi is digitized for use in meas uring the received signal strength . this signal can also be used to generate a loss of signal (los) alarm, with a pre - set hystere sis for assert and de - assert levels. the los assert threshold can be adjusted using the los level dac. alternatively, the los alarm can be programmed to detect the amplitude of the ac signal, the optical modulation amplitude (oma) at the receiver input. the oma los assert threshold can be adjusted using the rx amp dac. 4.2.1. input stage configuration the differential rxin inputs from the rosa can be terminated to a common mode voltage. this should be used for all recommended application frequencies of the phy1071 - 01 , where the inputs are ac coupled. the common mode voltage should be connected by setting rx_dccouple = 0 (e8h rxcontrol0 bit 3). 4.2.2. rate selection figure 12 - low pass filter rate selection a programmable low pass filter provides band limiting in the received signal path. the filter bandwidth is set to 0.75 x signal data rate for optimum signal to noise performance and is controlled by a 3 - bit con trol word as shown in table 1. the rate selection register, ratesel , stores two 3 - bit codes for controlling the filter; code a in bits 0 to 2, and code b in bits 3 to 5. the selection between the two codes is determin ed by the ratesel pin and the s oft rat e select bit as shown in figure 12 . thus, the ratesel pin can be used to switch between two pre - selected rates. the ratesel register is unique in that it is directly accessible from the 2 - wire serial slave interface. write accesses are routed to both the register in hardware and the ram. read accesses read the ratesel value from the hardware. this enables the phy1071 - 01 to respond more quickly to updates of this register. this also means that during the initialisation sequence, the bandwidth of the receiver can be set up before the dsfail alarm is cleared (see section 5.2.2) . this feature does not exist in the 2 - wire serial master interface. when loading registers from eeprom, ratesel is loaded via ram in the same way as all other registers. signal out ratesel f5h 0 - 2 ratesela rateselb ratesel programmable low-pass filter bit 3 soft rate select stat_con 1 0 signal in 6eh 3 - 5 3 downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 14 table 1 - signal data rates supported by the low pass filter 4.2.3. cml output stage configuration the cml output stage has two slew rate settings. for maximum receiver eye opening set cmlslew = 0 (e8h rxcontrol0 bit 0). to minimise emitted radiation set cmlslew = 1. the slew rates are defined in the table of parametric performance characteristics for the r eceive limiting amplifier (s ection 3 .3.1). the signal swing can also be adjusted. set hiloswing = 1 (e9h rxcontrol1 bit 1) for higher amplitude differential output swing as defined in the table in section 3 .3.1. set hiloswing = 0 for lower amplitude o utput swing. 4.2.4. loss of signal rxin+ rssi rx amp dac oma based los rxin- e8h bit 2 bit 1 lospolarity lostype rxcontrol0 amplitude detect los level dac power detect rx power adc oma_los_set f3h rxpoweradc fbh avg_los_set f4h mean rx power based los 1 0 los los stat_con 6eh bit 1 figure 13 - control of the los pin loss of signal (los) is determined in one of two ways. if lostype = 1 then the optical modulation amplitude (oma) method is selected. the signal amplitude measured at rxin+/ - is compared against a threshold level set by the oma_los_set register. if the oma does not exceed the threshold then the los pin and consequently the los bit in stat_con will be asserted. if lostype = 0 then the mean received power based method is selected. the signal power detec ted on the receiver signal strength indicator (rssi) pin is compared against a threshold level set by avg_los_set . if the rssi does not exceed the threshold then the los pin and los bit are ass erted. the polarity of the los pin is controll ed by lospolarity . if lospolarity = 0 then los is set high during a loss of signal condition. conversely, if lospolarity = 1 then los is set high when a signal is detected. bit 2 1 0 data rate 0 0 0 125/155 mbps 0 0 1 622 mbps 0 1 0 1062 mbps 0 1 1 1250 mbps 1 0 0 2125 mbps 1 0 1 n/a 1 1 0 n/a 1 1 1 n/a downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 15 register dac step size threshold range avg_los_set los level dac (8 bits) for codes 00h C 1fh step size = 1 a for codes 1f h C 7eh step size = 4 a 0 a to 3 1 a 31 a to 41 1 a oma_los_set rx amp dac (8 bits) use codes 0ah to c8 step size = 250 v (nominal dac range = 0mv to 64mv) 10mv to 5 0mv table 2 - los dac characte ristics for measurement of rssi, which is used by sff - 8472 digital diagnostics monitoring, the phy1071 - 01 can be connected as shown in figure 14, sourcing the photodiode bias current. this shows a phy109 3 tia i nterfacing to the phy1071 - 01 . the p hotodiode used is biased using the regulated output of the phy1071 - 01 , providing a stable an d low noise bias for the photodiode . the phy1071 - 01 measures the photodiode current and generates a report of received signal strength via an on board a - d converter. rxin+ amp programmable programmable low pass filter & output buffer los adc rssi los overload r f dc restore 50 ? 50 ? agc amp voltage regulator pda filt rx+ rx- vcc gnda pdc 100 ? amplifier rxout- rxout+ phy1071-01 3.3v rxin- amp los signal detect & - vcc gnda amplifier phy1093 los dac photodiode regulator 100 ? 1nf figur e 14: connection to tia for rssi method of los detection in some cases the tia may source an output current which is proportional to the received signal strength. in this case the application circuit shown in figure 15 should be used. the current i brssi b is mirrored using a dual npn transistor as shown. this sinks an o utput current from the phy1071 - 01 which can then be measured using the on chip dac. rx_in+ amp programmable programmable low pass filter & output buffer los adc rssi los overload voltage regulator pda rx+ rx- vcc gnda pdc 100 ? rx_out- rx_out+ phy1071-01 3.3v rx_in amp los - vcc gnda amplifier tia los dac photodiode regulator bc848cdw1t1 or similar i rssi figure 15: connection to tia with integrated rssi output downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 16 4.3. transmitter features the transmitter input buffer provides the necessary drive to the vcsel dri ver output stage . it is designed to be ac - coupled, with an internal 10 0 ? differential termination . the vcsel driver output is designed to drive vcsels in both common - cathode and common - anode configuration s , using either ac or dc coupling. t he driver circuit delivers a maximum peak to peak modulation current of 16 ma. the ma ximum current delivered in dc - coupled mode is dependent on the vcsel impedance. the voltage swing must remain in the compliance range of the output stage as specified in section 3. 4.2. the phy1071 - 01 vcsel driver operates with an analog mean - power control loop, which is digitally programmed using the mean power dac. modulation current is controlled by a vcsel modulation dac with the characteristics shown in table 3 . the modulation dac has a 75 a/bit resolution which suggests an upper limit of 19.1ma at full scale, however the modulation output stage is rated to 16ma over operating temperature and voltage . to satisfy the digital diagnostics requirements, the mean power, as represented by the mon itor photocurrent, is measured using the current monitor analogue to digital converter (tx power a dc ). the bias current a dc (tx bias adc) samples the vcsel bias current. register dac step size range tx_power_set mean power dac (8 bits) 12 a (actual da c range 0a to 3060a) 0 to 3ma modulationdacdefault vcsel modulation dac p 1 p (8 bits) 75 a (actual dac range 0.5ma to 19.1ma) 0ma to 16ma 1 range of modulation current measured at vcsel+/- (jitter within spec) table 3 - characteristics of the modulation and bias current dacs 4.3.1. bias current control e0h 1 - 2 kselect txcontrol1 dfh bit 1 loop_bw txcontrol0 mpd tx power adc fdh vcsel_bias tx_power_set f2h txbiasadc fch tx power adc mean power dac comp kfactor tx bias adc figure 16 - control registers affecting the apc loop the vcsel bias current is controlled by the mean - power control loop in which the current from the monitor photodiode in the tosa is compared with a reference current controlled by tx_power_set . the mean - power control loop can be configured for either common - cathode or common anode vcsels using the mpc_polarity bit of the txcontrol0 (dfh) register. note: the comparator is sensitive to large step changes in the value written to tx_power_set (or a small step change at low values). this can cause the safety critical shutdown module to assert a tx_fault, as will writing zero to tx_power_set . loop gain is affected by the coupling coefficient (kfactor) between the vcsel and m onitor photodiode. a configurable gain stage is included in the apc loop to compensate for this kfactor. the kselect bits control the gain stage and should be set up according to table 4. for example, for a tosa with k factor of 1/100 (vcsel bias current = 15ma, monitor diode current = 0.15ma) set kselect = 01. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 17 kselect 1 0 coupling coefficient 0 0 1/500 C 1/150 0 1 1/150 C 1/50 1 0 1/50 C 1/25 1 1 1/25 C 1/8 table 4 - gain settings for the apc loop the bandwidth of the control loop response can be controlled with loop_bw . for a critically damped loop, set loop_bw to 0. for a more rapid response, set loop_bw to 1. the frequency response of t he loop is detailed in section 3.4.3 vcsel mean power control loop. 4.3.2. modulation current control the modulation current can be controlled in two ways: set modlutdisab (dfh txcontrol0 bit5) to 1 to directly access the modulation dac. then, adjust modulation current by writing to modulationdacdefault ( d5 h ). set modlutdisab to 0to enable the modulation current vs. temperature look - up table (lut) in the phy1071 - 01 . the 45 byte lut is indexed by the value in temperature adc (feh), where index is given by: index = ( temperatureadc x 45) / 255 and the index rounds down to the lower temperature. w hen the lut is switched from the enabled to disabled state, the last control value from the lut will persist. o n disabling the lut the m odulation dac will not revert back to a value previously written to modulationdacdefault . a new value must be explicitly written to modulationdacdefault once the lut has been disabled. on power up the modulation dac will not be programmed with the value uploaded from the eeprom and will default to taking the value from the lut for the measured temperature. 4.3.3. vcsel driver se tup there is a trimming network on the output driver which adjusts the time constant for output damping on vcsel . it is controlled by the value in txdrivercap (f6h) which is used to select between 1 and 8 capacitors connected to the vcsel outputs as sh own in figure 17 . all capacitors are ~0.8pf. set txdrivercap to '00 h ' for no damping and fastest edge s; set to ffh for full damping and slowest edges. c c c c c vcsel +/- from modulation driver bit 4 bit 3 bit 2 bit 1 bit 0 c c bit 7 bit 6 bit 5 c figure 17 - time constant selection for the tx output damping network. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 18 4.4. vcsel safety features the vcsel safety circuitry monitors the device for potential faults . if a fault is detected, the safety logic turns off the transmitter bias and modulation currents and indicates the fault condition at pin tx_fault. the vcsel output driver can be disabled in one of four ways: 1. the tx_disable pin is taken high. 2. the internal safety critical shutdown circuitry detects a fault with a. the apc loop or bias current b. power supply 2.7v>vdd or vdd>3.9v c. rref shorted to ground, vdd or open circuit 3. the soft tx disable bit in st at_con is asserted 4. the watchdog timer times out, indicating that communication with the host/mcu h as been interrupted. in all cases the modulation current and the current to the vcsel_bias pin will be disabled, and the shutdown pin will be asserted. the purpose of the shutdown pin is to provide a means by which the vcsel can be isolated from ground (common cathode configuration) when an electr ical fault is detected. in cases 2 and 4, tx_fault will also be set. safety critical shutdown circuit dfhbit 6 hardware_ignore txcontrol0 e1h bit 7 hostsfttxfault txcontrol2 6eh bit 2 tx fault stat_con 6eh bit 6 soft tx disable stat_con e0h bit 3 sdpolarity txcontrol1 controller shutdown tx_fault shutdownpassword 7ah vcsel_bias vdd fet eg. short circuit bit 7 tx disable state gnd figure 1 8 - tx_fault and shutdown pin control logic 4.4.1. phy1071 - 01 fault management the safety critical shutdown circuit will shutdown and isolate the vcs el if it senses a fault with the bias current, the supply voltage or the reference voltage. for example, consider a vcsel arranged in common catho de configuration . the vcsel anode connects to the vcsel_bias pin and the cathode connects to ground. if a short circuit to vdd occurs on the route between the anode and vcsel_bias then the safety critical shutdown circuit will switch off the bias current. however, this will not protect the laser as a current path from vdd to ground still exists. a fet device can provide the required isolation when switched off by the shutdown pin as shown in figure 1 8 . the shutdown pin is controlled by the same signal which switches off the bias current. the shutdown pin output response to faults and polarity setting is shown in table 6. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 19 in common anode configuration the polarity of the shutdown pin needs to be rev ersed. the polarity of the shutdown pin is controlled by sdpolarity . the safety critical shutdown circuit can be disabled in software by setting hardware_ignore = 1, and entering the value 42h to the shutdownpassword register. in this case the vcsel will not be disabled when a fault is detected; however, a tx_fault will still be reported. this feature should be used with great caution as the eye safety features of the device will be disabled. the phy1071 - 01 will respond t o tx_disable being set even if hardware_ignore is set. power supply and vref faults result in the tx_fault latching and the laser being disabled momentarily. once the fault condition is removed the laser will be reactivated, however t he tx_fault output must be cleared by toggling tx_disable (or soft tx disable ). an apc loop fault results in the tx_fault latching and the laser being disabled. tx_disable (or soft tx disable ) must be pulsed high as shown in figure 5 to remove this latching condition and reactivate the laser. when the laser is turned on, during power up or after a fault, there will be a short period during which the bias cont rol loop is allowed to settle (t_settle, see section 3.4.3) before the safety control loop circuit is enabled. fault status sdpolarity (txcontrol2, bit 3) shutdown pin voltage no fault 0 high 1 low fault 0 low 1 high table 5 C shutdown output voltage under fault/no fault conditions 4.4.2. mcu and host fault management the mcu is responsible for maintaining and reporting alarms and warnings in acc ordance with the sff - 8472 specification. when an alarm is triggere d, the mcu must set host sfttxfault = 1. this will cause the phy1071 - 01 to report a fault on the tx_fault pin and in the stat_con register. the phy1071 - 01 will not disable the vcsel at this point. the mcu or the host could disable t he vcsel when a tx fault is detected in stat_con by asserting soft tx disable . 4.4.3. watchdog a watchdog is implemented by the phy1071 - 01 to monitor the activity of the attached mcu in digital diagnostics mode. when watchdogen (e1h txcontrol2 bit0) is set to 1, the phy1071 - 01 s wat chdog feature is enabled . the mcu is required to increment the watchdog[0:5] counter (e1h txcontrol2 ) at least every 100ms . if no change is detected in the counter , the phy1071 - 01 will disable the vcsel and will assert tx_fault. the vcsel wil l be re - enabl ed, and tx_fault de - asserted when either the watchdog counter is incremented, or the watchdog feature is disabled by writing 0 to watchdogen . on power up the watchdog feature is disabled. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 20 4.5. tsense temperature sensor the temperature is determined by measuring the ? v bbe b across an external transistor connected to the tsense pin. the transistor can be any standard npn silicon transistor with a beta > 100 connected i n diode mode (base and collector tied together). phyworks recommends using a bc847 or s imila r. calibration and averaging of the temperature sensor reading s using an external microcontroller are required to optim ise the accuracy. once optim i sed, the phy1071 - 01 can report temperature to sff8472 requirements over the recommended operating conditions. the temperature sensor operating range and corresponding tsense input levels are shown in table 6. symbol unit minimum maximum temperature t c - 70 +115 t sense diffe rential input voltage be v mv 50 100 table 6 C temperature sensor operating r ange tsense temperature adc signal conditioning switching current generator i 10ua i 200ua ? v be f igure 1 9 C temperature sensor functional block d iagram downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 21 5. control interface the phy1071 - 01 can be operated in one of two modes as dictated by the design of the module. the phy1071 - 01 will identify the mode by attempting to read from its 2 - wire serial eeprom interface (see section 5.4 ) on power up. if no eeprom is present then diagnostic mode is inferred. in digital diagnostics mode, the micro controller unit (mcu) and eeprom (address a0h) prese nt an sff - 8472 com pliant interface to the host. the mcu provides read/write acc ess to all registers in the a2 h registers map, calculates digital diagnostics monitor values and maintains al arms and warnings. the mcu must initialise the phy1071 - 01 control registers from eeprom, relay control information to the phy1071 - 01 , and fetch status information in real time. in stand - alone mode, the phy1071 - 01 is initiali sed directly from an external 4 kbit (8 x 512 bit) serial eeprom. serial id information as specified in the sfp msa is acces sible via the two wire interface . this mode supports temperature compensation of modulation current using a look - up table stored in eeprom. figure 20 - optical transceiver module configurations 5.1. memory map figure 21 - memory map for a 2g sfp or sff transceiver module containing a phy1071 - 01 device figure 21 shows the memory map of a module containing a phy1071 - 01 . an 8 kbit memory space is a natural step up from the minimum 4 kbit memory space required for sff - 8472 compliance, providing additional space in which to map the device settings registers of the phy1071 - 01 . the internal ram of the phy1071 - 01 implements the sff - 8472 diagnostics table and the device settings table. selection between tables is achieved using the tableselect (tabsel) register located at address offset 7fh. to access the diagnostics table, first write 00h to tabsel. to access the dev ice settings table, first wr ite 03h to tabsel. mcu a2h eeprom phy1071 - 01 rosa tosa a0h eeprom twi phy1071 - 01 rosa tosa a0h + a2h eeprom twi digital diagnostic mode stand alone mode sff -8472 serial id serial id (96) vendor specific (32) sff -8472 reserved (128) a0 h sff -8472 diagnostics sfp msa diag (120) vendor specific (7) phy1071-01 expansion eeprom undefined (127) phy1071-01 expansion eeprom undefined (127) sff -8472 u. eeprom user eeprom (120) vendor specific (8) phy1071-01 expansion eeprom undefined (128) a2 h tabsel = 00h or 01h device settings (128) tabsel tabsel tabsel 7fh a2 h tabsel = 02h a2 h tabsel = 03h downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 22 tabsel is effectively write - only because to write to tabsel has the effect of switching to a different r egister table. thus, reading tabsel will not yield the value which was previously wri tten. 5.2. operation scl reset 2-wire serial interface slave eeprom sa_sda 2-wire serial interface master ram controller hardware registers stat_con 6eh host or mcu sda sa_scl arbiter 2 1 3 alarmbytephy1071 78h testcontrol 79h modulationdacdefault d5h txpowerdown d6h rxpowerdown dbh txcontrol dfh-e1h diagnosticsselect e7h e8h-e9h rxcontrol f1h-f4h dacs f5h ratesel f6h txdrivercap fbh-ffh adcs 7fh tableselect figure 22 - serial interfaces to ram and the on - chip controller 5.2.1. data transfer m echanisms three distinct data paths are identified in f igure 22. when the phy1071 - 01 comes out of reset, the 2- wire serial slave interface is disabled. only path 1 is active. t he controller instructs the 2- wire serial master interface to attempt to transfer a2h register tables (sff - 8472 diagnostics and device settings) from the external eeprom to ram. if this is successful then the phy1071 - 01 will operate in stand - alone mode. if the transfer fails, then the dsfail and eerxfail alarm bits in the alarmbytephy1071 (78h) register will be set and the phy1071 - 01 will operate in diagnostics mode. regardless of the outcome, when the eeprom read process is complete the controller e nables the 2- wire serial slave interface. the 2- wire serial master interface is then no longer used. the 2- wire serial slave interface has slave address a2h. in diagnostics mode, the host or external mcu uses the 2- wire serial slave interface to write to or read from copies of the device settings held in r am. when the boot sequence is complete, the controller transfers data between the ram and the actual registers implemented in hardware periodically every 10ms. in stand - alone mode the ram space is not used once the boot sequence is complete. readi ng from a2h will return zero. path 3 is a special case which supports modules designed for stand - alone mode, enabling them to be set up or re - configured via the 2- wire serial interface slave. the phy1071 - 01 can be force d into diagnostic mode if the data integrity numbers in the eeprom are deliberately erased (see section 5.4 .2). this enables the host/ mcu to access both the ram (path 2) and the eeprom (path 3). all accesses to the a0h address space are directed to the eeprom only. accesses to the a2h address space are examined as they arrive by the 2- wire serial slave module, which in turn instructs the arbitration logic. the destination for the transaction depends on the value of tabsel and the register address as shown in t able 7 . downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 23 access type tabsel address range p 1 p destination memory read 00 lower ram read 03 upper ram write 00 lower ram + eeprom write 00 upper eeprom write 03 upper ram 1 addresses 00h to 7fh = lower. addresses 80h to ffh = upper. table 7 - destination of 2- wire serial interface transactions as a function of tab s el and address. 5.2.2. device i nitialisation s equence the initialisation sequence is illustrated in figure 23 . the data_ready_bar bit in the stat_con register indicates when data from the adcs may be read after power up. it is first set to 1 before the 2- wire serial slave interface is enabled to indicate that the phy1071 - 01 is not ready. once initialisation is complete and the adc data is ready data_ready_bar is cleared to 0. this event can be used by the external host/ mcu as a signal that the phy1071 - 01 is ready for device settings to be uploaded from the mcu to the phy1071 - 01 ram. the phy1071 - 01 will not enter the main diagnostic function loop until the upload is complete. this is initiated by the host/ mcu clearing the dsfail and eerxfail bits in the alarmbytephy1071 (78h) register. when dsfail is cleared and the main loop is executed the contents of ram will be transferred into the hardware registers of the phy1071 - 01 . downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 24 success? power up transfer a2h registers from eeprom to ram disable 2-wire serial slave interface set dsfail alarm bit.disable the vcsel. set data_ready_bar. yes no diagnostic mode stand-alone mode enable 2-wire serial slave interface 40 ms delay 40 start the 10ms poll timer read adcs wait 10 wait 10 update txfault pin.update stat_con register. clear data_ready_bar. wait dsfail set? yes no diag main update txfault pin andstat_con register based on hardware status. transfer ram content tohardware registers. erase ram. disable the vcsel. set data_ready_bar. enable 2-wire serial slave interface 15 ms delay start the 10ms poll timer 10 wait read adcs 10 wait index lut using temp adcvalue. transfer value to modulation dac. enable vcsel s-a main 15 25 when data_ready_bar iscleared, the host/mcu can start to upload a2h register settings to the phy1071-01 10 the phy1071-01 waits for thehost/mcu to finish the upload. when the upload is complete the host/mcu clears the dsfail bit. wait for analogue circuits tofinish initializing. time delay, ms figure 23 - phy1071 - 01 initialisation sequence. time delays for key stages are shown in ms. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 25 5.2.3. polling l oop t imer figure 24 - phy1071 - 01 polling loop timer function. a polling loop timer is implemented in the controller which expires every 10 ms. this is used to schedule functions in both the boot sequence and the main diagnostic and stand - alone operating modes. the wait clouds shown in the flow diagrams represent the sequence of events shown in f igure 24. the reset timer is the timer enabled by wdinhibit in the diagnosticsselect register (e7h). refer to the registers map for details. the checksum function is executed in diagnostic mode only. the phy1071 - 01 will generate a checksum of the device settings ram area by addition of each of the bytes listed in table 8, and store the result in the 16 bit ddmchecksum register (e5h to e6h) in big endian format. the checksum will allow the mcu to efficiently verify that the copies of these registers in the phy1071 - 01 and in its own memory are coherent. addr ess size (bytes) name 80h 40 reserved a8h 45 currentlut d6h 1 txpowerdown d7h 4 undefined dbh 1 rxpowerdown dch 3 undefined e8h 2 rxcontrol f1h 1 vref f2h 1 t x_power_set f3h 1 oma_los_set f4h 1 avg_los_set f5h 1 ratesel table 8 - registers included in the checksum calculation mbist selected restart the poll timer. (refresh the reset timer) yes no wait no timer expired yes no calculate checksum (diagnostic mode only) enter memory bist mode downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 26 5.2.4. controller m ain application loop f unctions figure 25 - phy1071 - 01 diagnostic mode main loop function. figure 26 - phy1071 - 01 stand - alone mode main loop function. lut enabled yes no check for tx faults, and set txfault pin if fault detected. process watchdog timer wait 10 watchdog expired transfer control data fromram to registers, and status from registers to ram. when the soft tx disable bit iscopied from ram to hardware, the vcsel will be re-enabled if the bit is 0. diag main read adcsperform slope adjust write to ddm registers index lut using temp adcvalue. transfer value to modulation dac. update stat_con register value stored in ram. yes no slope adjusted versions of theadc values are provided at a2h addresses 60h to 69h. reset the timer if the watchdogcounter has been incremented. lut enabled yes no s-a main index lut using temp adcvalue. transfer value to modulation dac. although only the temperaturevalue is required, the act of reading all adc values automatically triggers the next conversion. wait 10 read adcs. store tempadc value only. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 27 5.3. digital diagnostics m ode 5.3.1. introduction when used in digital diagnostic mode the phy1071 - 01 contains all of the necessary analogue and digital circuitry to generate the real time values required for sff - 8472 ddm reporting compliance. the power sup ply voltage , t emperature , txbias, mpd and rssi are all sampled using an on board a/d converter . t he digitised values are then made available over the slave 2 - wire serial interface , such that they can be used in conjunction with sff - 8472 calibration constan ts , to provide the host user with the following five real time reports: supply voltage, temperature, tx bias current, tx output power and rx input power. 5.3.2. on chip analogue to di g ital converter the phy1071 - 01 contains a single successive approximation adc , c omprising an 8 - bit dac followed by a selectable gain stage. the gain stage is either linear or multi - slope , depending on the select ed input from one of the five physical parameters being sampled. the multi - slope stage enables the adc to cover the very larg e dynamic range required for reporting tx and rx optical power within the sff - 8472 limits , using only 8 - bits to cover an equivalent 12 - bit dynamic range. the adc conversion time takes approximately 1ms. 5.3.3. adc characteristics ddm name adc input nominal range step size accuracy supply voltage v dd 1.7v to 4.4v 10.6 mv 3% temperature t emperature - 70c to +115c phy1071 - 01 = 0.8 3 c 3c tx bias txbias 0.0ma to 25.5ma 0.1ma 5% tx power mpd 0.0 a to 2448.0 a 1 a : 0.0 a to 32.0 a 5% 4 a: 32.0 a t o 416.0 a 16ua: 416.0 a to 2448.0 a rx power rssi 0.0 a to 2448.0 a 1ua: 0.0 a to 32.0 a 5% 4ua: 32.0 a to 416.0 a 16ua: 416.0 a to 2448.0 a table 9 C adc electrical characteristics 5.3.4. 3- slope adc tx and rx power ddm reports are represented by an 8 bit (0 - 255) adc value even though the overall dynamic range for both of these parameters is 0 a to 2448 a. a linear coding scheme would only provide 9.5 a resolution at low currents. acceptable low current resolution coupled with wide dyna mic range is possible by using a multi - slope gain stage within the adc circuitry. the following formulae are used to convert the 8 - bit adc (0 to 255) value into a linear pseudo 12 - bit adc (0 to 2448) value: 0 < adc 32: adc_l = adc 32 adc 128 adc_l = ((adc C 32) * 4) + 32 128 adc 255 adc_l = ((adc C 128) *16) + 416 downloaded from: http:///
phy1070 - 01 - rd - 1. 2 released datasheet page 28 0 50 100 150 200 250 0 500 1000 1500 2000 tx mpd current / rx rssi current (ua) adc value (dec) figure 27 C 3- slope adc function 5.3.5. adc ddm register locations t he 8 - bit adc values can be accessed in their raw format at addresses fbh to ffh (tabsel = 03h). th e adc values are also accessible at addresses 60h to 69h (tabsel = 00h) where tx power and rx power adc values are linearised by the phy1071 - 01 and, therefore, do not require any conversion from 3 - slope format unlike the raw 8 - bit adc values. u an external mcu is required to apply the correct calibration slope and offset values to the phy1071 - 01 adc ddm reports in order that the real time reports are meaningful u . table 10 shows the memory locations that should be addressed on the 2 - wire slave interface to access the various d dm adc values. all 8 bit or 12 bit adc values are left aligned into the 16 bit registers with unused bits set to zero. for example the msbit of tx output power is located at the msbit of 66h (tabsel = 00h). address location name size table select byte ( 7f) = 00h a2h 60h to 61h temperature 16 - bit a2h 62h to 63h vcc 16 - bit a2h 64h to 65h tx bias 16 - bit a2h 66h to 67h tx power 16 - bit a2h 68h to 69h rx power 16 - bit table select byte ( 7f) = 03h a2h fbh r xpower adc 8- bit a2h fch t xbiasadc 8- bit a2h fdh t xpower adc 8- bit a2h feh t emperature adc 8- bit a2h ffh vdd adc 8- bit table 10 C adc ddm register locations downloaded from: http:///
phy1070 - 01 - rd - 1. 2 released datasheet page 29 5.4. stand - alone m ode in stand - alone mode, the phy1071 - 01 is initiali sed directly from an external 4 kbit (8 x 512 bit) serial eeprom. serial id info rmation as specified in the sfp msa is accessible via the 2 - wire serial interface . this mode supports temperature compensation of modulation current using a look - up table stored in eeprom. 5.4.1. data integrity c hecking the (read - only) adcs located at addresses fbh to ffh are dual - functioned with (write - only) data integrity registers as follows: addr register value(hex) fbh fch fdh feh ffh serialeepromidentifier0 serialeepromidentifier1 serialeepromidentifier2 serialeepromchecksum0 serialeepromchecksum1 1bh 2ch 3dh or 4eh p -- p -- ppp table 1 1 - mapping of the data integrity numbers on power - up, the phy1071 - 01 will attempt to load its ram from the eeprom. if this is unsuccessful then eerxfail and dsfail are both set to 1 (78h alarmbyte phy1071 ) and initialisatio n will be stalled. if the transfer is successful then the integrity of the data will be checked. the phy1071 - 01 checks that the data read from eeprom at addresses fbh to fd h matches the values shown in t able 11. if there is a mismatch then dsfail is set t o 1 and initialisation will be stalled. if serialeepromidentifier2 = 3d then the phy1071 - 01 will accumulate a 16 bit checksum for the a2h ram address range 00h to fah (excluding 7fh). if this accumulated checksum does not compare correctly wit h the two serialeepromchecksum bytes, then dsfail will be set to 1 and initialisation will be stalled. once all checks are complete, if no alarms have been set then the hardware register s in the phy1071 - 01 are updated from the ram. data in ram addresses fbh to ffh will subsequently be overwritten by the adcs. 5.4.2. device s etup if a module is powered up with a blank or corrupted eeprom then the data integrity checking will fail and initialisation is stalled. however, the phy1071 - 01 can be forced into a setup mode if t he dsfail alarm is cleared by the host. this then permits the device to be configured and the eepro m written in - system. t o reconfigure or analyse a module with its eeprom already written, writing zero to th e data integrity register addresses in eeprom wil l have the effect of forcing the phy1071 - 01 into setup mode the next time it is powered up. 5.4.3. writing to eeprom the addressing of the ram in the phy1071 - 01 is consistent with the memory map for the module as a whole (see f igure 21 ). the table containing the sff - 8472 diagnostics registers is selected by tabsel = 0 and the table containing the device settings registers is selected by tabsel = 3. the serial eeprom connected to a phy1071 - 01 in stand alone mode is typically small and is organised as shown below: downloaded from: http:///
phy1070 - 01 - rd - 1. 2 released datasheet page 30 figure 28 - physical mapping of register tables into the eeprom in the stand - alone mode the device settings area in eeprom is effectively stored in the address range normally oc cupied by the sff - 8472 user ee prom (in diagnostics mode). when writing to device settings two separate write transactions are required: one write (into ram) with tabsel = 3, and one writ e (into eeprom) with tabsel = 0. phyworks recommends that the write protect functionality of the eeprom is utilised to ef fectively protect stored settings after programming. sff -8472 dia gnostic sfp msa diag (120) vendor specific (8) device settings (128) sfp msa serial id (256) 00h 80h ffh 00h 80h ffh mapped to a0h mapped to a2h downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 31 5.5. 2- wire serial interface the phy1071 - 01 has a pair of 2 - wire serial interfaces - a slave for interfacing to an external mcu for use in diagnostics mode and a master for interfacing to an external eeprom for use in stand - alone mode. both interfaces communicate using the protocol described in this section. 5.5.1. framing and data transfer the two - wire interface comprises a clock line (scl) and a data line (sda). w hen the bus is idle both are pulled high within the phy1071 - 01 by 8 k ? pull - ups. an individual transaction is framed by a start condition and a stop condition. a start condition occurs when a bus master pulls sda low while the clock is high. a stop condition occ urs when the bus master allows sda to transition low - to - high when the clock is high. within the frame, the master has exclusive control of the bus. the phy1071 - 01 does not support repeat start conditions whereby the master may simultaneously end one frame and start another without releasing the bus by replacing the stop condition with a start condition. within a frame, the state of sda may only change when scl is low. a data bit is transferred on a low - to - high transition of scl. data is arranged in packets of 9 bits. the first 8 bits represent data t o be transferred (most significant bit first). the last bit is an acknowledge bit. t he recipient of the data holds sda low during the ninth clock cycle of a data packet to ack nowledge (ack) the byte. leaving sda to float high on the ninth bit signals a not - acknowledged (nack) condition. the interpretation of the acknowledge bit by the sender will depend on the type of transaction and the nature of the byte being received. 5.5.2. device a ddressing the first byte to be sent after a start condition is an address byte. the first seven bits of the by te contain the target slave address (msb first). the eighth bit indicates the tr ansaction type C 0 = write, 1 = read. each slave interface on the bus is assigned a 7 - bit slave address. if no slave matches the address broadcast by the master then sda will be left to float high during the acknowledge bit and the master receives a nack. the master must then assert a stop condition. if a slav e identifies the address then it acknowledges the master and proceeds with the transaction identified by the ty pe bit. the slave interface of the phy1071 - 01 can decode slave addresses a0h and a2h. msb 7 6 4 5 3 2 1 0 start nack stop r/w address sda scl figure 2 9 - address decoding example C slave not available 5.5.3. write t ransaction figure 30 shows an example of a write transaction. the address byte is successfully acknowledged by the slave, and the type bit is set low to signify a write transaction. after the acknowledge the mas ter sends a single data byte. all signalling is controlled by the master except for the sda line during the acknowledge bits. during the acknowledge the direction of the sda line is reversed and the slav e pulls sda low to return a 0 (ack) to the master. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 32 figure 30 - write transaction if the slave is unable to receive data then it should return a nack after the dat a byte. this will cause the master to issue a stop and thus terminate the transaction. the phy1071 - 01 interprets the first data byte as a register address. this will be used to set an internal memory pointer. subsequent data bytes within the same transaction will then be written to the memory location addressed by the pointer. the pointer is auto - incremented after each byte. there is no limit to the number of bytes which may be written in a single burst to the 256 byte internal ram of the phy1071 - 01 . if the slave is not ready to receive a byte then it may hold scl low immediatel y after the acknowledge bit. when scl is released the master starts to send the next byte. this is known as clock stretching. the phy1071 - 01 slave interface will not clock stretch at up to100 khz scl frequency. 5.5.4. read t ransaction figure 31 - read transaction figure 31 shows an example of a 2 byte read transaction. the address byte is successfully acknowledged by the slave, and the type bit is set high to signify a read. af ter the ack the slave returns a byte from the location identified by the internal memory pointer. this pointer is then auto - incremented. the slave then releases sda so that the master can ack the byte. if the s lave receives an ack then it will send another byte. the master identifies the last byte by sending a nack to the slave. the maste r then issues a stop to terminate the transaction. thus, to implement a random access read transaction, a write must first be issued by the m aster containing a slave address byte and a single data byte (the register address) as shown in f igure 30 . this sets up the memory pointer. a read is then sent to retrieve data from this add ress (see figure 31 ). 7 1 start ack stop sda scl 4 3 2 1 0 w 7 6 5 msb ack sda direction to slave from slave 7 1 start ack stop sda scl r nack sda direction to slave from slave 7 0 7 0 ack downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 33 6. register map all phyworks specific registers are listed in this section. for details of other regi sters refer to the sff - 8472 specification for diagnostic monitoring interface for optical transcei ve rs. where a single power - on reset (por) value is shown for a range of addresses , that value applies to all bytes in the range. note that the power on reset values may be overwritten during initialisation by the mcu (or from eeprom in stand - alone mode). for registers containing a single 8 - bit field, the most significant bit of the field is stored in bit 7 of the reg ister byte. multi - byte registers are stored in big - endian order unless specified otherwise. note that reserved or internal use only register bits are specified as read only. these registers should not change from their por default settings. 6eh st at_con status and control register for some sff - 8472 functions bit field name type por 7 tx disable state r 0 digital state of the tx disable input pin. updated within 100msec of change of pin. 6 soft tx disable r/w 0 read/write bit that allows software disable of laser. writing 1 disables laser. this bit is ord with the hard tx_disable pin value. 5 reserved r 0 reserved for future use. 4 rx rate select state r 0 digital state of the sfp rx rate select input pin. updated within 100msec of change on pin. 3 soft rx rate select r/w 0 soft rx rate select read/write bit that allows software rx rate select. writing 1 selects full bandwidth operation. this bit is ord with the rate_select pin value. 2 tx fault r 0 digital state of the tx_fault output pin. updated within 100msec of change on the pin. 1 los r/w 0 digital state of the los output pin. updated within 100msec of change on the pin. 0 data_ready_bar r 0 indicates phy1071 - 01 has achieved power up and data is ready. bit remains high until d ata is ready to be read at which time the device sets the bit low. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 34 78h alarmbytephy1071 status register for the phy1071 - 01 control module. bit field name type por 7 wd4 r 0 this counter records the number of times that the phy1071 - 01 has reset its elf due to an internal timeout. the timer is controlled by wdinhibit in the diagnosticsselect register. 6 wd3 r 0 5 wd2 r 0 4 wd1 r 0 3 wd0 r 0 2 membistpassed r 0 built - in self test (bist) result (1 = passed ) from memory test initiated by test control register bit 1. 1 dsfail r/w 0 data structure corrupt (1 = data integrity bytes read from eeprom during power up are incorrect). clearing this bit during initialisation is necessary in order to allow the phy1071 - 01 to resume its normal mission mode functions. 0 eerxfail r 0 eeprom dma load fail (1 = no response from eeprom during power up) 79h testcontrol this register puts the device into various test modes and should not be written to during normal operation. it should always have val ue 0. bit field name type por 7 atbcontrol5 r/w 0 analog test bus control bit0 6 atbcontrol4 r/w 0 analog test bus control bit1 5 atbcontrol3 r/w 0 analog test bus control bit2 4 atbcontrol2 r/w 0 analog test bus control bit3 3 atbcontrol1 r/w 0 a nalog test bus control bit4 2 atbcontrol0 r/w 0 analog test bus control bit5 1 startmemorybist r/w 0 set to 1 to initiate memory built - in self test (mbist) 0 scantestmode r/w 0 set to 1 to enter scan test mode. 7ah shutdownpassword set to 42h to pr event the safety critical shutdown logic from disabling the vcsel when a hardware fault is detected (see also txcontrol0). type r/w por 00h 7bh - 7eh reserved -- type r por 00h downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 35 7fh tableselect indirect addressing for register tables. 00h selects th e sff - 8472 diagnostics and user eeprom register tables. 03h selects the phy1071 - 01 device settings table. note that data read from this register is not valid. type r/w por 00h 80h C a7h reserved -- type r por 00h a8h C d4h currentlut modulation curr ent vs. temperature look - up table (lut). the 45 entry lut is indexed using the temperatureadc as follows: (temperatureadc x 45) / 255. type r/w por 00h d5h modulationdacdefault controls the modulation current (dac) when the lut is disabled. during powe r up, the temperature is sampled and the dac is re - loaded with a value from the lut. type r/w por 00h d6h txpowerdown selectively turns off the power supply to circuits in the transmitter module. 0 = power on. 1 = power off. bit field name type po r 7 vddmeaspwrd r/w 0 - 6 termpwrd r/w 0 - 5 dacpwrd r/w 0 power down dac 4 driverpwrd r/w 0 power down vcsel driver 3 txbiaspwrd r/w 0 power down transmit bandgap bias + current gen. (this will completely disable the ic). 2 dbuffapwrd r/w 0 power down data buffer 1 temppwrd r/w 0 power down temperature sensor 0 safetypwrd r/w 0 power down safety logic d7h - dah undefined -- type r por 00h downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 36 dbh rxpowerdown selectively turns off the power supply to circuits in the receiver module. 0 = power on. 1 = power off. bit field name type por 7 limitpwrd r/w 0 power down limiter 6 filtpwrd r/w 0 power down rx filter 5 compspwrd r/w 0 adc comparator powerdown 4 ampdetpwrd r/w 0 power down amplitude detector 3 regpwrd r/w 0 power down regulator 2 agcpwrd r/w 0 power down agc amp 1 cmlpwrd r/w 0 power down cml (rx related) 0 rxbiaspwrd r/w 0 power down receiver bandgap bias + current gen. dch - deh undefined -- type r por 00h dfh txcontrol0 control bits for the transmitter circuits. bit field name type por 7 osc_mon r/w 0 multiplexes the internal oscillator onto tx_fault pin for monitoring (oscillator = 1, normal operation = 0) 6 hardware_ignore r/w 0 soft disable for safety critical shutdown. set to 1 t o prevent vcsel shutdown when the scs circuits detect an electrical fault and asserts a tx fault condition. 5 modlutdisab r/w 0 modulation current lut loop control (disable lut = 1) 4 sfttxfault r/w 0 (internal use only. set to 0.) 3 dac_ready r/w 0 (internal use only. set to 0.) 2 testbw r/w 0 (internal use only. set to 0.) 1 loop_bw r/w 0 controls the average power control loop response. set to 0 for critical damping. 0 mpc_polarity r/w 1 this must match the configuration of the tosa. for common anode connection, set to 1. common cathode = 0. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 37 e0h txcontrol1 control bits for the transmitter circuits. bit field name type por 7 test_comp_hiz r 0 (internal use only. set to 0.) 6 test_compout_en r 0 (internal use only. set to 0.) 5 test_compout r 0 (inte rnal use only. set to 0.) 4 test_koff r 0 (internal use only. set to 0.) 3 sdpolarity r/w 1 controls the polarity of the sd pin. (for sd pin = 0 for shutdown, set sdpolarity = 1 ). 2 kselect1 r/w 0 kselect[1:0] selects one of four gain settings for a gain stage in the aut omatic power control loop (see t able 4 ). this optimises the loop gain for the coupling coefficient of the tosa. 1 kselect0 r/w 0 0 tempsel3i r 0 (internal use only. set to 0.) e1h txcontrol2 control bits for the transmitter c ircuits. bit field name type por 7 hostsfttxfault r/w 0 set to 1 to assert a tx fault condition on the tx_fault pin. 6 watchdog5 r/w 0 when the watchdog counter is enabled, it must be incremented at least once every 100ms. if this does not occur then the phy1071 - 01 will disable the vcsel and assert a tx fault condition. incrementing the counter or disabling the watchdog will cause normal operation to resume. 5 watchdog4 r/w 0 4 watchdog3 r/w 0 3 watchdog2 r/w 0 2 watchdog1 r/w 0 1 watchdog0 r/w 0 0 watchdogen r/w 0 watchdog function enable (enable = 1) e2h - e4h txcontrolspare reserved type r por 00h e5hC e6h ddmchecksum 16 - bit checksum updated by the phy1071 - 01 every 10ms. see section 5.2.3 for a detailed description. type r por 00h downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 38 e7h diagnosticsselect diagnostic functions (for internal use) are controlled by this register. bit field name type por 7 - 0 spare 6 - r 0 spare 5 - r 0 spare 4 - r 0 spare 3 - r 0 spare 2 - r 0 spare 1 wdinhibit r/w 0 see also register 78h a larmbyte phy1071 . set to 1 to disable the timer and prevent the chip from resetting itself if the timer is not serviced. set to 0 for normal operation. 0 tstclksel r/w 0 set to 1 to select the sa_sda pin as the clock source for the digital macro inst ead of the internal oscillator. e8h rxcontrol0 control bits for the receiver circuits. bit field name type por 7 ampdet _dcfbdisable r 0 (internal use only. set to 0.) 6 gc_disable r 0 (internal use only. set to 0.) 5 agcdcfb_disable r 0 (intern al use only. set to 0.) 4 trimsel r/w 0 (internal use only. set to 0.) 3 rx_dccouple r/w 0 for ac coupled input, set to 0 to terminate the differential signal at rxin+/ - to a common mode voltage. set to 1 when the inputs are dc coupled. 2 lospol arity r/w 0 los pin sense (1=signal detect;0=loss of signal) 1 lostype r/w 0 los detection type (1=oma;0=mean rx power) 0 cmlslew r/w 0 rxout+/ - slew rate control. set to 0 for a fast slew rate . set to 1 for slow slew rate. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 39 e9h rxcontrol1 c ontrol bits for the receiver circuits. bit field name type por 7 - r 0 spare 6 - r 0 spare 5 - r 0 spare 4 lorv r 0 (internal use only. set to 0.) 3 fosctrim1 r 0 (internal use only. set to 0.) 2 fosctrim0 r 0 (internal use only. set to 0.) 1 hiloswing r/w 0 controls the differential swing of the signal output on rxout+/ - (1 = high amplitude, 0 = low amplitude) 0 lim_dcfbdisable r 0 (internal use only. set to 0.) eah - efh rxcontrolspare reserved type r por 00h f0h undefined -- type r por 00h f1h vref reference voltage trim dac. the reference voltage can be set by adjusting vref until the desired voltage is seen at pin rref. rref is pulled to ground by a 10 k ? resistor for a 1v reference. type r/w por 71h f2h tx_power_set sets the tx mean power loop reference monitor current dac. this dac therefore controls the average output power of the vcsel . type r/w por 00h f3h oma_los_set sets the threshold level for optical measurement amplitude based los detection. type r/w por 00h f4h avg_los_set sets the threshold level for receiver signal strength indicator (rssi) based los detection. type r/w por 00h downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 40 f5h ratesel controls the bandwidth of the programmable low pass filter in the receiver. the two rate selection fields a and b enable switching between two different bandwidths using the ratesel pin. bit field name type por 7 osc1 r/w 0 (internal use only. set to 0.) 6 osc0 r/w 0 (internal use only. set to 0.) 5 rateselb2 r/w 0 rate selection b. selects one of five cut- off f requency settings (see table 1 ). 4 rateselb1 r/w 0 3 rateselb0 r/w 0 2 ratesela2 r/w 0 rate selection a. selects one of five cut- off f requency settings (see table 1 ). 1 ratesela1 r/w 0 0 ratesela0 r/w 0 f6h txdrivercap selects between different time constants for the trimming network which controls the tx driver output damping (see figure 17 ). type r/w por 00h f7h - fah reserved -- type r por 00h fbh rxpoweradc this register is dual functioned. reads received optical power , rx ad c value. writes data integrity value serialeepromidentifier0. type r/w por 00h fch txbiasadc this register is dual functioned. reads vcsel bias , tx bias adc value. writes data integrity value serialeepromidentifier1. type r/w por 00h fdh txpowera dc this register is dual functioned. reads transmit optical power , tx power adc value. writes data integrity value serialeepromidentifier2. type r/w por 00h feh temperatureadc this register is dual functioned. reads module temperature adc value. write s data integrity value serialeepromchecksum0. type r/w por 00h downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 41 ffh vdd adc this register is dual functioned. reads power supply , vdd adc value. writes data integrity value serialeepromchecksum1. type r/w por 00h downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 42 7. simplified interface models x predrive+/- out+out- vdd x 50 50 v cm x txin+txin- f igure 3 2- transmit input structure figure 3 3- transmit output structure vdd x 50 50 v cm rxin+rxin- vdd x rxout+rxout- 50 50 vdd x vdd x figure 3 4- receive input structure figure 3 5- receive output structure downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 43 ibias vdd x imon vdd x figure 3 6- mpd input structure figure 3 7- vcsel bias output structure vdd x pdreg vdd x los, txfault figure 3 8- los/tx_fau lt output figure 3 9- rssi regulator output structure downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 44 8. typical applications phy1071-01 sa_sda 12 3 4 5 6 7 8 9 10 19 20 21 22 23 24 25 26 27 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 sa_scl reset from mcu vdd_rxo vss_rx rxout- rxout+ sda scl rref +3.3v 100nf 10nf10nf 10k ? tx_fault +3.3v host board 4.7k ? tx_disable high speed100 ? differential 2-wire serialinterface to/from microcontroller from host (sfp connector) vss_tx txin+ txin- 10nf 10nf vss_tx ratesel nc mpd vss_txvdd_tx vdd_txovcsel_bias vcsel- vcsel+ vss_tx vgg vdd_tx +3.3v 100nf 100nf +3.3v +3.3v +3.3v +3.3v from host (sfp connector) 30k ? high speed 100 ? differential vdd_rxvss_rx rxin- rxin+ los rssi tsense shutdown 10nf 10nf 4.7k ? +3.3v high speed 100 ? differential rosa pd bias bc847bor similar hostboard 100nf +3.3v blm15bd102blm15bd102 blm15bd102 c pf load ? series ? r ? 100 ? 1nf 5% 0.125wsmt0402 blm15bd102 ferrite bead, supplier:murata 10nf 100nf optionalshutdown fet figure 40 C phy1071 - 01 in ddm mode downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 45 phy1071-01 sa_sda 12 3 4 5 6 7 8 9 10 19 20 21 22 23 24 25 26 27 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 sa_scl reset vdd_rxo vss_rx rxout- rxout+ sda scl rref +3.3v 100nf 10nf10nf 10k ? tx_fault +3.3v host board 4.7k ? tx_disable high speed100 ? differential 2-wire interface used toset-up the phy1071-01 and program eeprom attached to pins 1 & 36. from host(sfp connector) vss_tx txin+ txin- 10nf 10nf vss_tx ratesel nc mpd vss_txvdd_tx vdd_txovcsel_bias vcsel- vcsel+ vss_tx vgg vdd_tx +3.3v 100nf 100nf +3.3v from host (sfp connector) 30k ? high speed 100 ? differential vdd_rxvss_rx rxin- rxin+ los rssi tsense shutdown 10nf 10nf 4.7k ? +3.3v high speed 100 ? differential bc847bor similar hostboard 100nf +3.3v 5% 0.125wsmt0402 12 3 4 5 6 7 8 gnd a2 a1 a0 sda scl wp vcc +3.3v 4k eeprom (512 x 8) at24c04 or similar blm15bd102 ferrite bead, supplier:murata no connection +3.3v +3.3v +3.3v blm15bd102blm15bd102 blm15bd102 c pf load ? series ? r ? 10nf 100nf optionalshutdown fet rosa pd bias 100 ? 1nf figure 41 C phy1071 - 01 in stand alone mode 8.1. power supply c onnections the phy1071 - 01 has been designed as a low power device. in order to achieve low operating power consumption the transmitter and receiver circuitry in the phy1071 - 01 share some common internal bias circuitry. this requires that the phy1071 - 01 transmitter and receiver be powered up together for correct operation. powering up the transmitter vdds and not the receiver vdds , or the reverse, will not damage the phy1071 - 01 but will cause the part to function incorrectly. 8.1.1. power supply f iltering although the tx vdds and rx vdds should be powered together and therefore , ult imately be connected at a common node , it is beneficial to separately filter the power supplies for the tx vdd and rx vdd supplies. separately filtering the transmitter and receiver supplies off chip will reduce power supply noise and cross talk between the transmitter and receiver C it is generally good practice to separately filter and decouple the individual supplies on any multifunction ic. in addition to supplying separate ly filtered supplies to the tx vdds and rx vdds of the phy1071 - 01 , it is also rec ommended that any other ics and digital circuitry connected to the phy1071 - 01 in an application environment (e.g. sfp module) be suitably filtered and decouple d also. an example of this would be to supply a filtered digital supply for the external mcu , req uired to compliment the phy1071 - 01 in ddm sff - 8472 applications. downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 46 12 3 4 5 6 7 8 9 10 19 20 21 22 23 24 25 26 27 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 vdd_rxo vss_rx rref rx vdd 10k ? vss_tx vss_tx vss_txvdd_tx vdd_txo vss_tx vgg vdd_tx 1.0uf +3.3v vdd_rxvss_rx ferrite rx vdd txvdd txvdd txvdd centre ground paddle pcb via connect to ground plane ferrite 0.1uf 0.1uf 0.1uf 0.1uf tx vdd rx vdd pin 3 pin 35 pin 20/21 pin 27 tx vdd and rx vdd should be separatelyfiltered and well decoupled. a single +3.3v connection should be used to power both tx vdd and rx vdd using a star topology filter scheme as shown above. the phy1071-01 tx vdds and rx vdds should not be independently powered to avoid conduction between tx and rx vdd esd diode circuits. figure 4 2 C recommended power supply connections and filtering. 8.1.2. power - on - reset the phy1071 - 01 features an internal power - on - reset function that applies a reset to the internally digital logic once the supply voltage reaches a preset value (>2.0v). the internal power - on - reset typically takes 27ms after power has been applied based on a 50ms slow start voltage ramp. the phy1071 - 01 may be reset externally by applying a logic high pulse to the reset pin. this is useful to guarantee the state of the phy1071 - 01 logic when using the device in conjunction with an external mcu . downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 47 9. packaging figure 41 - qfn 36 package outline drawing downloaded from: http:///
phy1071 - 01 - rd - 1. 2 released datasheet page 48 maxim cannot assume responsibility for use of any circuitry other than circuitry enti rely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, inc. 160 rio robles , sunnyvale, ca 94086 408 - 737 - 7600 ? 2012 maxi m integrated products maxim is a registered trademark of maxim integrated products, inc. 10. c ontact information for technical support, contact maxim at www.maxim - ic.com/support . disclaimer this datasheet contains preliminary information and is subject to change. the phy107 1- 01 contains circuitry to aid the implementation of eye safety functions i n equipment using laser devices. phyworks ltd accepts no liability for failure of this function in this product nor for injur y to persons as a result of use of this product. testing of the function ality of eye safety circuits in equipment using this product is the responsibility of the manufacturer of the equipment. this document does not transfer or license any intellectual property ri ghts to the user. phyworks ltd assumes no liability or warranty for infringement of patent, copyright or other intellect ual property rights through the use of this product . phyworks ltd assumes no liability for fitness for particular use or claims arisi ng from sale or use of its products. phyworks ltd products are not intended for use in life critical or sustai ning applications. downloaded from: http:///

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